1. Field of the Invention
Example embodiments relate to semiconductor memory devices, and more particularly, to a memory test system including a semiconductor memory device suitable for testing an on-die termination, and method thereof.
2. Description of the Related Art
Generally, semiconductor memory devices, e.g., Dynamic Random Access Memory (DRAM), may be tested for detecting defects in a wafer process and in a packaging process. In order to reduce test time, a parallel test, in which a plurality of semiconductor memory devices may be tested at once, may be employed. One form of parallel testing may be a merged-data line scheme. During the merged-data line scheme, at least two output pins of the semiconductor memory devices may be combined, and a selected output data may be provided to a tester through the combined output pins.
As design and process of the semiconductor memory devices become more developed, a double data rate (DDR) DRAM may be used. In case of DDR DRAM having over 200 MHz, for example, a termination circuit may be used for preventing distortion of signals during transmission of data. A termination technique may include a motherboard termination technique and an on-die termination technique. The motherboard termination technique may be when the termination circuit is located on a mother board. The on-die termination technique may be when the termination circuit is located on a die. Because signal integrity of the on-die termination technique may be higher than that of the mother board termination technique, the on-die termination technique may generally be used.
In a read mode, the on-die termination circuit may be deactivated. In a write mode, the on-die termination circuit may function as a termination resistor. Further, as an operating speed of the semiconductor memory devices may be increased, an efficient test of the on-die termination circuit may also be required.